Online Resume


Christophe Guerrier

I have 21+ years experience as a Microelectronic Engineer, specialized in physical implementation of Integrated Circuits, covering pure analog layout (RF to mixed signals) and digital implementation (multi-millions gates design with clock going up to 2Ghz).

During my career, I have contributed to the development of several chips using nodes from 0.5um down to 5nm ; and worked with cross-continental and multicultural teams under tight schedules.

I have consistently up-skilled myself, seeking opportunities to learn and develop myself. exploring new areas, like moving from pure Analog to Digital Design. I have some experience in Project Management. I am fast learner, a much appreciated team contributor. My various roles required me to effectively communicate across multi-functional teams, show rigorous work and methodology and being able to work autonomously.

I undertook a Higher Diploma in Statistics to sharpen my data analysis abilities. In the future, I would like to merge my knowledge of IC design with my statistical knowledge.

Skills & Proficiency

IC ANALOG LAYOUT
Expert
IC PHYSICAL DESIGN
Expert
DIGITAL PNR
Expert
Cadence VIRTUOSO (XL)
Expert
DRC/LVS/PEX/ERC
Expert
STA
Expert
PrimeTime
Expert
Tempus
Advanced
ICC
Expert
Redhawk
Advanced
Encounter
Expert
Perl
Advanced
Tcl
Advanced
Python
Advanced
Statistics
Intermediate
Data Analysis
Intermediate
R
Intermediate

Experience and Education

  • Synopsys 2024 - Present
    Dublin, Ireland
    Physical Design Engineer
  • Renesas Aug 2021 - present
    Dublin, Ireland
    Principal (Snr) Physical Design Engineer
    Renesas bought Dialog in 2021
  • S3Semi - Adesto - Dialog 2018 - 2024
    Dublin, Ireland
    Principal (Snr) Physical Design Engineer
  • ICMaskdesign 2014 - 2018
    Maynooth, Ireland
    Senior Layout Engineer
  • UCD 2013 - 2014
    Dublin, Ireland
    H-Dip Statistics
  • Freelance contractor 2013
    Cambridge, UK
    Analog Layout contractor for Samsung
    Dusseldorf, Germany
    Analog Layout contractor for Toshiba
  • Intel 2005 - 2012
    Shannon, Ireland
    Physical Digital Design Engineer
  • Analog Devices 2005
    Limerick, Ireland
    Senior Layout Engineer
  • Dolphin Integration 2001 - 2004
    Grenoble, France
    Layout Engineer
  • Universite Blaise Pascal 1998 - 2001
    Clermont-Ferrand, France
    Msc (DESS) Microelectronic Analogic
    Bsc (Maitrise) Physics
    Bsc (Licence) Physics

Node and technology Exposure

350 nm
180 nm
130 nm
90 nm
65 nm
45 nm
40 nm
32 nm
28 nm
22 nm
16 nm FinFet
12 nm FinFet
7 nm FinFet
3 nm and below